Job Summary:

The position will be responsible for verifying soft IPs for a number of different Lattice FPGA families. The candidate should be able to create test plan, design and architect testbench, do functional simulation, analyze and debug the design, communicate all findings to design team, and extract verification metrics to sign-off the design. The ideal candidate is also expected to work on improving soft IP verification process via automation and scripting.

The candidate will develop comprehensive verification plans, clear metrics and continuously measure progress again the plan throughout the project. Testing can be done by writing Verilog or UVM testbench and running simulations or perform hardware validation on an actual FPGA device. He/she is also expected to develop verification components as needed. The ideal candidate may also act as a technical lead and help develop best practices and world class methods for verification.

Requirements:

• BS or MS in Computer/Electronics/Electrical Engineering with 10+ years of design verification experience
• 10+ years experience in Digital Design and Verification, Verilog, System Verilog, C/C++ is ideal
• Knowledge of the following through education and/or experience:
  • UVM, assertion-based, and constraint-random verification
  • Verilog, C/C++, Python

• Expertise in DDR, PCIe, Ethernet, AMBA, and serial communication protocols is desired
• Domain Knowledge in Machine Learning, Embedded System, Video and Audio systems a big plus
• Good teamwork and able to collaborate with multi-site teams
• Good written and verbal communication skills

Company industry: Semiconductor